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List of semiconductor scale examples
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Listed are many semiconductor scale examples for various metal–oxide–semiconductor field-effect transistor (MOSFET, or MOS transistor) semiconductor manufacturing process nodes.
Timeline of MOSFET demonstrations
PMOS and NMOS
| Date | Channel length | Oxide thickness | MOSFET logic | Researcher(s) | Organization | Ref | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| [20,000 nm](20-mm-process) | [100 nm](100-nm) | PMOS | Mohamed M. Atalla, Dawon Kahng | Bell Telephone Laboratories | ||||||||||||||||
| NMOS | ||||||||||||||||||||
| [10,000 nm](10-mm-process) | nm | PMOS | Mohamed M. Atalla, Dawon Kahng | Bell Telephone Laboratories | ||||||||||||||||
| NMOS | ||||||||||||||||||||
| 8,000 nm | 150 nm | NMOS | Chih-Tang Sah, Otto Leistiko, A.S. Grove | Fairchild Semiconductor | ||||||||||||||||
| [5,000 nm](6-mm-process) | [170 nm](180-nm-process) | PMOS | ||||||||||||||||||
| [1,000 nm](1-mm-process) | PMOS | Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu | IBM T.J. Watson Research Center | |||||||||||||||||
| 1973 | 7,500 nm | NMOS | Sohichi Suzuki | NEC | title=1970s: Development and evolution of microprocessors | url=http://www.shmj.or.jp/english/pdf/ic/exhibi748E.pdf | website=Semiconductor History Museum of Japan | access-date=27 June 2019}} | ||||||||||||
| [6,000 nm](6-mm-process) | PMOS | Toshiba | title=1973: 12-bit engine-control microprocessor (Toshiba) | url=http://www.shmj.or.jp/english/pdf/ic/exhibi739E.pdf | website=Semiconductor History Museum of Japan | access-date=27 June 2019}} | ||||||||||||||
| 1,000 nm | [ nm](45-nm-process) | NMOS | Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu | IBM T.J. Watson Research Center | ||||||||||||||||
| [500 nm](500-nm-process) | ||||||||||||||||||||
| [1,500 nm](1-5-mm-process) | [ nm](22-nm-process) | NMOS | Ryoichi Hori, Hiroo Masuda, Osamu Minato | Hitachi | last1=Kubo | first1=Masaharu | last2=Hori | first2=Ryoichi | last3=Minato | first3=Osamu | last4=Sato | first4=Kikuji | title=1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers | chapter=A threshold voltage controlling circuit for short channel MOS integrated circuits | date=February 1976 | volume=XIX | pages=54–55 | doi=10.1109/ISSCC.1976.1155515 | s2cid=21048622 }} | |
| [3,000 nm](3-mm-process) | NMOS | Intel | ||||||||||||||||||
| 1,000 nm | [25 nm](28-nm-process) | NMOS | William R. Hunter, L. M. Ephrath, Alice Cramer | IBM T.J. Watson Research Center | ||||||||||||||||
| [100 nm](130-nm-process) | [5 nm](5-nm) | NMOS | Toshio Kobayashi, Seiji Horiguchi, K. Kiuchi | Nippon Telegraph and Telephone | ||||||||||||||||
| 150 nm | [2.5 nm](3-nm-process) | NMOS | Toshio Kobayashi, Seiji Horiguchi, M. Miyake, M. Oda | Nippon Telegraph and Telephone | ||||||||||||||||
| [75 nm](90-nm-process) | NMOS | Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis | MIT | |||||||||||||||||
| [60 nm](65-nm-process) | NMOS | Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis | MIT | last1=Chou | first1=Stephen Y. | last2=Smith | first2=Henry I. | last3=Antoniadis | first3=Dimitri A. | title=Sub-100-nm channel-length transistors fabricated using x-ray lithography | journal=Journal of Vacuum Science & Technology B: Microelectronics Processing and Phenomena | date=January 1986 | volume=4 | issue=1 | pages=253–255 | doi=10.1116/1.583451 | bibcode=1986JVSTB...4..253C | issn=0734-211X}} | ||
| 200 nm | [3.5 nm](5-nm-process) | PMOS | Toshio Kobayashi, M. Miyake, K. Deguchi | Nippon Telegraph and Telephone | ||||||||||||||||
| [40 nm](40-nm) | NMOS | Mizuki Ono, Masanobu Saito, Takashi Yoshitomi | Toshiba | |||||||||||||||||
| [16 nm](16-nm) | PMOS | Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba | NEC | |||||||||||||||||
| [50 nm](55-nm-process) | [1.3 nm](3-nm-process) | NMOS | Khaled Z. Ahmed, Effiong E. Ibok, Miryeong Song | Advanced Micro Devices (AMD) | ||||||||||||||||
| [6 nm](7-nm-process) | PMOS | Bruce Doris, Omer Dokumaci, Meikei Ieong | IBM | |||||||||||||||||
| [3 nm](3-nm-process) | PMOS | Hitoshi Wakabayashi, Shigeharu Yamagami | NEC | |||||||||||||||||
| NMOS |
CMOS (single-gate)
| Date | Channel length | Oxide thickness | Researcher(s) | Organization | Ref | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Chih-Tang Sah, Frank Wanlass | Fairchild Semiconductor | title=1963: Complementary MOS Circuit Configuration is Invented | url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ | website=Computer History Museum | access-date=6 July 2019}} | ||||||||||||||||||||||||||
| 1968 | 20,000 nm | [ nm](130-nm-process) | RCA Laboratories | last1=Lojek | first1=Bo | title=History of Semiconductor Engineering | date=2007 | publisher=Springer Science & Business Media | isbn=9783540342588 | page=330 | url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330}} | ||||||||||||||||||||
| 1970 | [10,000 nm](10-mm-process) | nm | RCA Laboratories | ||||||||||||||||||||||||||||
| [2,000 nm](3-mm-process) | A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. White | Mitel Semiconductor | |||||||||||||||||||||||||||||
| [3,000 nm](3-mm-process) | Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio Sakai | Hitachi Central Research Laboratory | title=1978: Double-well fast CMOS SRAM (Hitachi) | url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf | website=Semiconductor History Museum of Japan | access-date=5 July 2019}} | |||||||||||||||||||||||||
| [1,200 nm](1-5-mm-process) | [ nm](32-nm-process) | R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley | Intel | last1=Gealow | first1=Jeffrey Carl | title=Impact of Processing Technology on DRAM Sense Amplifier Design | url=https://core.ac.uk/download/pdf/4426308.pdf | publisher=Massachusetts Institute of Technology | via=CORE | date=10 August 1990 | pages=149–166 | access-date=25 June 2019}} | |||||||||||||||||||
| [900 nm](1-mm-process) | [ nm](16-nm-process) | Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima | Nippon Telegraph and Telephone (NTT) | last1=Mano | first1=Tsuneo | last2=Yamada | first2=J. | last3=Inoue | first3=Junichi | last4=Nakajima | first4=S. | title=1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers | chapter=Submicron VLSI memory circuits | date=February 1983 | volume=XXVI | pages=234–235 | doi=10.1109/ISSCC.1983.1156549 | s2cid=42018248 }} | |||||||||||||
| [1,000 nm](1-mm-process) | [ nm](28-nm-process) | G.J. Hu, Yuan Taur, Robert H. Dennard, Chung-Yu Ting | IBM T.J. Watson Research Center | ||||||||||||||||||||||||||||
| [800 nm](800-nm-process) | [17 nm](20-nm-process) | T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano | Matsushita | last1=Sumi | first1=T. | last2=Taniguchi | first2=Tsuneo | last3=Kishimoto | first3=Mikio | last4=Hirano | first4=Hiroshige | last5=Kuriyama | first5=H. | last6=Nishimoto | first6=T. | last7=Oishi | first7=H. | last8=Tetakawa | first8=S. | title=1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers | chapter=A 60ns 4Mb DRAM in a 300mil DIP | date=1987 | volume=XXX | pages=282–283 | doi=10.1109/ISSCC.1987.1157106 | s2cid=60783996 }} | |||||
| 700 nm | [12 nm](12-nm) | Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima | Nippon Telegraph and Telephone (NTT) | last1=Mano | first1=Tsuneo | last2=Yamada | first2=J. | last3=Inoue | first3=Junichi | last4=Nakajima | first4=S. | last5=Matsumura | first5=Toshiro | last6=Minegishi | first6=K. | last7=Miura | first7=K. | last8=Matsuda | first8=T. | last9=Hashimoto | first9=C. | last10=Namatsu | first10=H. | title=1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers | chapter=Circuit technologies for 16Mb DRAMs | date=1987 | volume=XXX | pages=22–23 | doi=10.1109/ISSCC.1987.1157158 | s2cid=60984466 }} | |
| [500 nm](500-nm) | [12.5 nm](14-nm-process) | Hussein I. Hanafi, Robert H. Dennard, Yuan Taur, Nadim F. Haddad | IBM T.J. Watson Research Center | ||||||||||||||||||||||||||||
| [250 nm](250-nm-process) | Naoki Kasai, Nobuhiro Endo, Hiroshi Kitajima | NEC | |||||||||||||||||||||||||||||
| 400 nm | [ nm](10-nm-process) | M. Inoue, H. Kotani, T. Yamada, Hiroyuki Yamauchi | Matsushita | last1=Inoue | first1=M. | last2=Kotani | first2=H. | last3=Yamada | first3=T. | last4=Yamauchi | first4=Hiroyuki | last5=Fujiwara | first5=A. | last6=Matsushima | first6=J. | last7=Akamatsu | first7=Hironori | last8=Fukumoto | first8=M. | last9=Kubota | first9=M. | last10=Nakao | first10=I. | last11=Aoi | title=1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers | chapter=A 16mb Dram with an Open Bit-Line Architecture | date=1988 | pages=246– | doi=10.1109/ISSCC.1988.663712 | s2cid=62034618 }} | |
| [100 nm](110-nm-process) | Ghavam G. Shahidi, Bijan Davari, Yuan Taur, James D. Warnock | IBM T.J. Watson Research Center | |||||||||||||||||||||||||||||
| 1993 | [350 nm](350-nm-process) | Sony | |||||||||||||||||||||||||||||
| 1996 | 150 nm | Mitsubishi Electric | |||||||||||||||||||||||||||||
| 1998 | [180 nm](180-nm-process) | TSMC | |||||||||||||||||||||||||||||
| [5 nm](5-nm) | Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa | NEC | url=http://www.thefreelibrary.com/NEC+test-produces+world's+smallest+transistor.-a0111295563 | title=NEC test-produces world's smallest transistor | website=Thefreelibrary.com | access-date=7 December 2017}} |
Multi-gate MOSFET (MuGFET)
| Date | Channel length | MuGFET type | Researcher(s) | Organization | Ref | ||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| DGMOS | Toshihiro Sekigawa, Yutaka Hayashi | Electrotechnical Laboratory (ETL) | |||||||||||||||||||||||||||||||||
| 1987 | [2,000 nm](3-mm-process) | DGMOS | Toshihiro Sekigawa | Electrotechnical Laboratory (ETL) | first1=Hanpei | last1=Koike | first2=Tadashi | last2=Nakagawa | first3=Toshiro | last3=Sekigawa | first4=E. | last4=Suzuki | first5=Toshiyuki | last5=Tsutsumi | title=Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode | journal=TechConnect Briefs | date=23 February 2003 | volume=2 | issue=2003 | pages=330–333 | s2cid=189033174 | url=https://pdfs.semanticscholar.org/1a31/399021f62ae3d00dd6dd42d2bc7483598d26.pdf | archive-url=https://web.archive.org/web/20190926013047/https://pdfs.semanticscholar.org/1a31/399021f62ae3d00dd6dd42d2bc7483598d26.pdf | url-status=dead | archive-date=26 September 2019 }} | ||||||||||
| [250 nm](250-nm-process) | DGMOS | Bijan Davari, Wen-Hsing Chang, Matthew R. Wordeman, C.S. Oh | IBM T.J. Watson Research Center | ||||||||||||||||||||||||||||||||
| [180 nm](180-nm) | |||||||||||||||||||||||||||||||||||
| GAAFET | Fujio Masuoka, Hiroshi Takato, Kazumasa Sunouchi, N. Okabe | Toshiba | |||||||||||||||||||||||||||||||||
| 200 nm | FinFET | Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda | Hitachi Central Research Laboratory | ||||||||||||||||||||||||||||||||
| [17 nm](20-nm-process) | FinFET | Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor | University of California (Berkeley) | last1=Tsu-Jae King | first1=Liu | author-link1=Tsu-Jae King Liu | title=FinFET: History, Fundamentals and Future | url=https://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse | website=University of California, Berkeley | publisher=Symposium on VLSI Technology Short Course | date=June 11, 2012 | access-date=9 July 2019 | archive-url=https://web.archive.org/web/20160528220227/http://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse | archive-date=28 May 2016 | url-status=live}} | ||||||||||||||||||||
| 2001 | [15 nm](16-nm-process) | FinFET | Chenming Hu, Yang-Kyu Choi, Nick Lindert, Tsu-Jae King Liu | University of California (Berkeley) | last1=Hu | first1=Chenming | author1-link=Chenming Hu | last2=Choi | first2=Yang-Kyu | last3=Lindert | first3=N. | last4=Xuan | first4=P. | last5=Tang | first5=S. | last6=Ha | first6=D. | last7=Anderson | first7=E. | last8=Bokor | first8=J. | last9=Tsu-Jae King | first9=Liu | title=International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224) | chapter=Sub-20 nm CMOS FinFET technologies | date=December 2001 | pages=19.1.1–19.1.4 | doi=10.1109/IEDM.2001.979526 | isbn=0-7803-7050-3 | s2cid=8908553 }} | |||||
| [10 nm](10-nm-process) | FinFET | Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor | University of California (Berkeley) | last1=Ahmed | first1=Shibly | last2=Bell | first2=Scott | last3=Tabery | first3=Cyrus | last4=Bokor | first4=Jeffrey | last5=Kyser | first5=David | last6=Hu | first6=Chenming | last7=Liu | first7=Tsu-Jae King | last8=Yu | first8=Bin | last9=Chang | first9=Leland | title=Digest. International Electron Devices Meeting | chapter=FinFET scaling to 10 nm gate length | date=December 2002 | pages=251–254 | doi=10.1109/IEDM.2002.1175825 | citeseerx=10.1.1.136.3757 | chapter-url=https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf | isbn=0-7803-7462-2 | s2cid=7106946 | access-date=2019-10-11 | archive-date=2020-05-27 | archive-url=https://web.archive.org/web/20200527205136/https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf | url-status=dead }} | |
| [3 nm](3-nm-process) | GAAFET | Hyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan Ryu | KAIST |
Other types of MOSFET
| Date | Channel | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| length | ||||||||||||||||||||||||||||
| (nm) | Oxide | |||||||||||||||||||||||||||
| thickness | ||||||||||||||||||||||||||||
| (nm) | MOSFET | |||||||||||||||||||||||||||
| type | Researcher(s) | Organization | Ref | |||||||||||||||||||||||||
| TFT | Paul K. Weimer | RCA Laboratories | ||||||||||||||||||||||||||
| GaAs | H. Becke, R. Hall, J. White | RCA Laboratories | ||||||||||||||||||||||||||
| 100,000 | [](130-nm-process) | TFT | T.P. Brody, H.E. Kunig | Westinghouse Electric | ||||||||||||||||||||||||
| FGMOS | Dawon Kahng, Simon Min Sze | Bell Telephone Laboratories | ||||||||||||||||||||||||||
| MNOS | H.A. Richard Wegener, A.J. Lincoln, H.C. Pao | Sperry Corporation | ||||||||||||||||||||||||||
| BiMOS | Hung-Chang Lin, Ramachandra R. Iyer | Westinghouse Electric | ||||||||||||||||||||||||||
| BiCMOS | Hung-Chang Lin, Ramachandra R. Iyer, C.T. Ho | Westinghouse Electric | ||||||||||||||||||||||||||
| 1969 | VMOS | Hitachi | title=Advances in Discrete Semiconductors March On | url=https://www.powerelectronics.com/content/advances-discrete-semiconductors-march | journal=Power Electronics Technology | publisher=Informa | pages=52–6 | access-date=31 July 2019 | date=September 2005 | archive-url=https://web.archive.org/web/20060322222716/http://powerelectronics.com/mag/509PET26.pdf | archive-date=22 March 2006 | url-status=live}} | ||||||||||||||||
| DMOS | Y. Tarui, Y. Hayashi, Toshihiro Sekigawa | Electrotechnical Laboratory (ETL) | ||||||||||||||||||||||||||
| ISFET | Piet Bergveld | University of Twente | last1=Bergveld | first1=P. | title=Development of an Ion-Sensitive Solid-State Device for Neurophysiological Measurements | journal=IEEE Transactions on Biomedical Engineering | date=January 1970 | volume=BME-17 | issue=1 | pages=70–71 | doi=10.1109/TBME.1970.4502688 | pmid=5441220 | bibcode=1970ITBE...17...70B }} | |||||||||||||||
| [1000](1-mm-process) | DMOS | Y. Tarui, Y. Hayashi, Toshihiro Sekigawa | Electrotechnical Laboratory (ETL) | |||||||||||||||||||||||||
| 1977 | VDMOS | John Louis Moll | HP Labs | |||||||||||||||||||||||||
| LDMOS | Hitachi | last1=Duncan | first1=Ben | title=High Performance Audio Power Amplifiers | date=1996 | publisher=Elsevier | isbn=9780080508047 | pages=[177–8, 406](https://archive.org/details/highperfomanceau0000dunc/page/177) | url=https://archive.org/details/highperfomanceau0000dunc/page/177}} | |||||||||||||||||||
| IGBT | Bantval Jayant Baliga, Margaret Lazeri | General Electric | ||||||||||||||||||||||||||
| [2000](3-mm-process) | BiCMOS | H. Higuchi, Goro Kitsukawa, Takahide Ikeda, Y. Nishio | Hitachi | |||||||||||||||||||||||||
| [300](350-nm-process) | K. Deguchi, Kazuhiko Komatsu, M. Miyake, H. Namatsu | Nippon Telegraph and Telephone | ||||||||||||||||||||||||||
| [1000](1-mm-process) | BiCMOS | H. Momose, Hideki Shibata, S. Saitoh, Jun-ichi Miyamoto | Toshiba | |||||||||||||||||||||||||
| [90](90-nm-process) | [8.3](10-nm-process) | Han-Sheng Lee, L.C. Puzio | General Motors | |||||||||||||||||||||||||
| [60](65-nm-process) | Ghavam G. Shahidi, Dimitri A. Antoniadis, Henry I. Smith | MIT | ||||||||||||||||||||||||||
| [10](10-nm-process) | Bijan Davari, Chung-Yu Ting, Kie Y. Ahn, S. Basavaiah | IBM T.J. Watson Research Center | last1=Davari | first1=Bijan | author1-link=Bijan Davari | last2=Ting | first2=Chung-Yu | last3=Ahn | first3=Kie Y. | last4=Basavaiah | first4=S. | last5=Hu | first5=Chao-Kun | last6=Taur | first6=Yuan | last7=Wordeman | first7=Matthew R. | last8=Aboelfotoh | first8=O. | first11=Michael R. | title=Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide | journal=1987 Symposium on VLSI Technology. Digest of Technical Papers | date=May 1987 | pages=61–62 | url=https://ieeexplore.ieee.org/document/4480422}} | |||
| [800](800-nm-process) | BiCMOS | Robert H. Havemann, R. E. Eklund, Hiep V. Tran | Texas Instruments | |||||||||||||||||||||||||
| [30](32-nm-process) | EJ-MOSFET | Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba | NEC | |||||||||||||||||||||||||
| 1998 | [32](32-nm) | NEC | ||||||||||||||||||||||||||
| 1999 | 8 | |||||||||||||||||||||||||||
| 8 | EJ-MOSFET | Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba | NEC |
Commercial products using micro-scale MOSFETs
Products featuring 20 μm manufacturing process
- RCA's CD4000 series of integrated circuits (ICs) beginning in 1968.
Products featuring 10 μm manufacturing process
Main article: 10 μm process
- Intel 4004, the first single-chip microprocessor CPU, launched in 1971.
- Intel 8008 CPU launched in 1972.
Products featuring 8 μm manufacturing process
- Intel 1103, an early dynamic random-access memory (DRAM) chip launched in 1970.
- MOS Technology 6502 1 MHz CPU launched in 1975.
Products featuring 6 μm manufacturing process
Main article: 6 μm process
- Toshiba TLCS-12, a microprocessor developed for the Ford EEC (Electronic Engine Control) system in 1973.
- Intel 8080 CPU launched in 1974 was manufactured using this process.
- The Television Interface Adaptor, the custom graphics and audio chip developed for the Atari 2600 in 1977.
- MOS Technology SID, a programmable sound generator developed for the Commodore 64 in 1982.
- MOS Technology VIC-II, a video display controller developed for the Commodore 64 in 1982 (5 μm).
Products featuring 3 μm manufacturing process
Main article: 3 μm process
- Intel 8085 CPU launched in 1976.
- Intel 8086 CPU launched in 1978.
- Intel 8088 CPU launched in 1979.
- Motorola 68000 8 MHz CPU launched in 1979 (3.5 μm).
Products featuring 1.5 μm manufacturing process
Main article: 1.5 μm process
- NEC's 64kb SRAM memory chip in 1981.
- Intel 80286 CPU launched in 1982.
- The Amiga Advanced Graphics Architecture (initially sold in 1992) included chips such as Alice that were manufactured using a 1.5 μm CMOS process.
Products featuring 1 μm manufacturing process
Main article: 1 μm process
- NTT's DRAM memory chips, including its 64kb chip in 1979 and 256kb chip in 1980.
- NEC's 1Mb DRAM memory chip in 1984.
- Intel 80386 CPU launched in 1985.
Products featuring 800 nm manufacturing process
Main article: 800 nm process
- NTT's 1Mb DRAM memory chip in 1984.
- NEC and Toshiba used this process for their 4Mb DRAM memory chips in 1986.
- Hitachi, IBM, Matsushita and Mitsubishi Electric used this process for their 4Mb DRAM memory chips in 1987.
- Toshiba's 4Mb EPROM memory chip in 1987.
- Hitachi, Mitsubishi and Toshiba used this process for their 1Mb SRAM memory chips in 1987.
- Intel 486 CPU launched in 1989.
- microSPARC I launched in 1992.
- First Intel P5 Pentium CPUs at 60 MHz and 66 MHz launched in 1993.
Products featuring 600 nm manufacturing process
Main article: 600 nm process
- Mitsubishi Electric, Toshiba and NEC introduced 16Mb DRAM memory chips manufactured with a 600nm process in 1989.
- NEC's 16Mb EPROM memory chip in 1990.
- Mitsubishi's 16Mb flash memory chip in 1991.
- Intel 80486DX4 CPU launched in 1994.
- IBM/Motorola PowerPC 601, the first PowerPC chip, was produced in 0.6 μm.
- Intel Pentium CPUs at 75 MHz, 90 MHz and 100 MHz.
Products featuring 350 nm manufacturing process
Main article: 350 nm process
- Sony's 16Mb SRAM memory chip in 1994.
- NEC VR4300 (1995), used in the Nintendo 64 game console.
- Intel Pentium Pro (1995), Pentium (P54CS, 1995), and initial Pentium II CPUs (Klamath, 1997).
- AMD K5 (1996) and original AMD K6 (Model 6, 1997) CPUs.
- Parallax Propeller, 8 core microcontroller.
Products featuring 250 nm manufacturing process
Main article: 250 nm process
- Hitachi's 16Mb SRAM memory chip in 1993.
- Hitachi and NEC introduced 256Mb DRAM memory chips manufactured with this process in 1993, followed by Matsushita, Mitsubishi Electric and Oki in 1994.
- NEC's 1Gb DRAM memory chip in 1995.
- Hitachi's 128Mb NAND flash memory chip in 1996.
- DEC Alpha 21264A, which was made commercially available in 1999.
- AMD K6-2 Chomper and Chomper Extended. Chomper was released on May 28, 1998.
- AMD K6-III "Sharptooth" used 250 nm.
- Mobile Pentium MMX Tillamook, released in August 1997.
- Pentium II Deschutes.
- Dreamcast console's Hitachi SH-4 CPU and PowerVR2 GPU, released in 1998.
- Pentium III Katmai.
- Initial PlayStation 2's Emotion Engine CPU.
Processors using 180 nm manufacturing technology
Main article: 180 nm process
- Intel Coppermine E- October 1999
- Sony PlayStation 2 console's Emotion Engine and Graphics Synthesizer – March 2000
- ATI Radeon R100 and RV100 Radeon 7000 – 2000
- AMD Athlon Thunderbird – June 2000
- Intel Celeron (Willamette) – May 2002
- Motorola PowerPC 7445 and 7455 (Apollo 6) – January 2002
Processors using 130 nm manufacturing technology
Main article: 130 nm process
- Fujitsu SPARC64 V – 2001
- Gekko by IBM and Nintendo (GameCube console) – 2001
- Motorola PowerPC 7447 and 7457 – 2002
- IBM PowerPC G5 970 – October 2002 – June 2003
- Intel Pentium III Tualatin and Coppermine – 2001-04
- Intel Celeron Tualatin-256 – 2001-10-02
- Intel Pentium M Banias – 2003-03-12
- Intel Pentium 4 Northwood- 2002-01-07
- Intel Celeron Northwood-128 – 2002-09-18
- Intel Xeon Prestonia and Gallatin – 2002-02-25
- VIA C3 – 2001
- AMD Athlon XP Thoroughbred, Thorton, and Barton
- AMD Athlon MP Thoroughbred – 2002-08-27
- AMD Athlon XP-M Thoroughbred, Barton, and Dublin
- AMD Duron Applebred – 2003-08-21
- AMD K7 Sempron Thoroughbred-B, Thorton, and Barton – 2004-07-28
- AMD K8 Sempron Paris – 2004-07-28
- AMD Athlon 64 Clawhammer and Newcastle – 2003-09-23
- AMD Opteron Sledgehammer – 2003-06-30
- Elbrus 2000 1891ВМ4Я (1891VM4YA) – 2008-04-27 http://www.mcst.ru/b_4-5.shtml
- MCST-R500S 1891BM3 – 2008-07-27 https://web.archive.org/web/20151101211823/http://www.mcst.ru/b_18-19.shtml
- Vortex 86SX – http://www.dmp.com.tw/
Commercial products using nano-scale MOSFETs
Chips using 90 nm manufacturing technology
Main article: 90 nm process
- Sony–Toshiba Emotion Engine+Graphics Synthesizer (PlayStation 2) – 2003
- IBM PowerPC G5 970FX – 2004
- Elpida Memory's 90 nm DDR2 SDRAM process – 2005
- IBM PowerPC G5 970MP – 2005
- IBM PowerPC G5 970GX – 2005
- IBM Waternoose Xbox 360 Processor – 2005
- IBM–Sony–Toshiba Cell processor – 2005
- Intel Pentium 4 Prescott – 2004-02
- Intel Celeron D Prescott-256 – 2004-05
- Intel Pentium M Dothan – 2004-05
- Intel Celeron M Dothan-1024 – 2004-08
- Intel Xeon Nocona, Irwindale, Cranford, Potomac, Paxville – 2004-06
- Intel Pentium D Smithfield – 2005-05
- AMD Athlon 64 Winchester, Venice, San Diego, Orleans – 2004-10
- AMD Athlon 64 X2 Manchester, Toledo, Windsor – 2005-05
- AMD Sempron Palermo and Manila – 2004-08
- AMD Turion 64 Lancaster and Richmond – 2005-03
- AMD Turion 64 X2 Taylor and Trinidad – 2006-05
- AMD Opteron Venus, Troy, and Athens – 2005-08
- AMD Dual-core Opteron Denmark, Italy, Egypt, Santa Ana, and Santa Rosa
- VIA C7 – 2005-05
- Loongson (Godson) 2Е STLS2E02 – 2007-04
- Loongson (Godson) 2F STLS2F02 – 2008-07
- MCST-4R – 2010-12
- Elbrus-2C+ – 2011-11
Processors using 65 nm manufacturing technology
Main article: 65 nm process
- Sony–Toshiba EE+GS (PStwo) – 2005
- Intel Pentium 4 (Cedar Mill) – 2006-01-16
- Intel Pentium D 900-series – 2006-01-16
- Intel Celeron D (Cedar Mill cores) – 2006-05-28
- Intel Core – 2006-01-05
- Intel Core 2 – 2006-07-27
- Intel Xeon (Sossaman) – 2006-03-14
- AMD Athlon 64 series (starting from Lima) – 2007-02-20
- AMD Turion 64 X2 series (starting from Tyler) – 2007-05-07
- AMD Phenom series
- IBM's Cell Processor – PlayStation 3 – 2007-11-17
- IBM's z10
- Microsoft Xbox 360 "Falcon" CPU – 2007–09
- Microsoft Xbox 360 "Opus" CPU – 2008
- Microsoft Xbox 360 "Jasper" CPU – 2008–10
- Microsoft Xbox 360 "Jasper" GPU – 2008–10
- Sun UltraSPARC T2 – 2007–10
- AMD Turion Ultra – 2008-06
- TI OMAP 3 Family – 2008-02
- VIA Nano – 2008-05
- Loongson – 2009
- NVIDIA GeForce 8800GT GPU – 2007
Processors using 45 nm technology
Main article: 45 nm process
- Matsushita released the 45 nm Uniphier in 2007.
- Wolfdale, Yorkfield, Yorkfield XE and Penryn are Intel cores sold under the Core 2 brand.
- Intel Core i7 series processors, i5 750 (Lynnfield and Clarksfield)
- Pentium Dual-Core Wolfdale-3M are current Intel mainstream dual core sold under the Pentium brand.
- Diamondville, Pineview are current Intel cores with hyper-threading sold under the Intel Atom brand.
- AMD Deneb (Phenom II) and Shanghai (Opteron) Quad-Core Processors, Regor (Athlon II) dual core processors https://www.amd.com/us-en/0,,3715_15503,00.html?redir=45nm01, Caspian (Turion II) mobile dual core processors.
- AMD (Phenom II) "Thuban" Six-Core Processor (1055T)
- Xenon in the Xbox 360 S model.
- Sony–Toshiba Cell Broadband Engine in PlayStation 3 Slim model – September 2009.
- Samsung S5PC110, as known as Hummingbird.
- Texas Instruments OMAP 36xx.
- IBM POWER7 and z196
- Fujitsu SPARC64 VIIIfx series
- Espresso (microprocessor) Wii U CPU
Chips using 32 nm technology
Main article: 32 nm process
- Toshiba produced commercial 32Gb NAND flash memory chips with the 32nm process in 2009.
- Intel Core i3 and i5 processors, released in January 2010
- Intel 6-core processor, codenamed Gulftown
- Intel i7-970, was released in late July 2010, priced at approximately US$900
- AMD FX Series processors, codenamed Zambezi and based on AMD's Bulldozer architecture, were released in October 2011. The technology used a 32 nm SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design.
- Ambarella Inc. announced the availability of the A7L system-on-a-chip circuit for digital still cameras, providing 1080p60 high-definition video capabilities in September 2011
Chips using 24–28 nm technology
- SK Hynix announced that it could produce a 26 nm flash chip with 64 Gb capacity; Intel Corp. and Micron Technology had by then already developed the technology themselves. Announced in 2010.
- Toshiba announced that it was shipping 24 nm flash memory NAND devices on August 31, 2010.
- In 2016 MCST's 28 nm processor Elbrus-8S went for serial production.
Chips using 22 nm technology
Main article: 22 nm process
- Intel Core i7 and Intel Core i5 processors based on Intel's Ivy Bridge 22 nm technology for series 7 chip-sets went on sale worldwide on April 23, 2012.
Chips using 20 nm technology
- Samsung Electronics began mass production of 64Gb NAND flash memory chips using a 20 nm process in 2010.
- Nvidia Tegra X1 (Nintendo Switch and Nvidia Shield TV)
Chips using 16 nm technology
- TSMC first began 16nm FinFET chip production in 2013.
- Nvidia Tegra X1+ (later Nintendo Switch and Nvidia Shield TV models)
Chips using 14 nm technology
Main article: 14 nm process
- Intel Core i7 and Intel Core i5 processors based on Intel's Broadwell 14 nm technology was launched in January 2015.
- AMD Ryzen processors based on AMD's Zen or Zen+ architectures and which uses 14 nm FinFET technology.
Chips using 10 nm technology
Main article: 10 nm process
- Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10nm process in 2013. On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm.
- TSMC began commercial production of 10 nm chips in early 2016, before moving onto mass production in early 2017.
- Samsung began shipping Galaxy S8 smartphone in April 2017 using the company's 10 nm processor.
- Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process in June 2017.
Chips using 7 nm technology
Main article: 7 nm process
- TSMC began risk production of 256 Mbit SRAM memory chips using a 7 nm process in April 2017.
- Samsung and TSMC began mass production of 7 nm devices in 2018.
- Apple A12 and Huawei Kirin 980 mobile processors, both released in 2018, use 7 nm chips manufactured by TSMC.
- AMD began using TSMC 7 nm starting with the Vega 20 GPU in November 2018, with Zen 2-based CPUs and APUs from July 2019, and for both PlayStation 5 and Xbox Series X/S consoles' APUs, released both in November 2020.
Chips using 5 nm technology
Main article: 5 nm process
- Samsung began production of 5 nm chips (5LPE) in late 2018.
- TSMC began production of 5 nm chips (CLN5FF) in April 2019.
Chips using 3 nm technology
Main article: 3 nm process
- TSMC have announced plans to release 3nm devices during 2021–2022.
- Samsung Electronics have begun risk production of 3 nm GAAFET transistors in June 2022.
- Apple A17 Pro (iPhone 15 Pro)
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