From Surf Wiki (app.surf) — the open knowledge base

14 nm process

MOSFET technology node

The 14 nanometer process refers to a marketing term for the MOSFET technology node that is the successor to the 22nm (or 20nm) node. The 14nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following 22nm was expected to be 16nm. All 14nm nodes use FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology.

Since at least 1997, process nodes have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, metal pitch or gate pitch on a 14nm device is fourteen nanometers. For example, TSMC and Samsung's 10 nm processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density, and TSMC's 7 nm processes are dimensionally similar to Intel's 10 nm process.

Samsung Electronics taped out a 14 nm chip in 2014, before manufacturing 10 nm class NAND flash chips in 2013. The same year, SK Hynix began mass-production of 16nm NAND flash, and TSMC began 16nm FinFET production. The following year, Intel began shipping 14nm scale devices to consumers.

History

Background

The resolutions of a 14 nm device are difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning are required.

A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick, but can also go up to about 100 nm. The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.

Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the 16 nm/14 nm node circa 2010. Samsung and Synopsys had also, at that time, begun implementing double patterning in 22 nm and 16 nm design flows. Mentor Graphics reported taping out 16 nm test chips in 2010. On January 17, 2011, IBM announced that they were teaming up with ARM to develop 14 nm chip processing technology.

On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the 14 nm manufacturing processes and leading-edge 300 mm wafers. The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips. On May 17, 2011, Intel announced a roadmap for 2014 that included 14 nm transistors for their Xeon, Core, and Atom product lines.

Technology demos

In the late 1990s, Hisamoto's Japanese team from Hitachi Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, including TSMC's Chenming Hu and various UC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17nm process. They later developed a 15nm FinFET process in 2001. In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated FinFET devices down to 10 nm gate length.

In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process. It had erstwhile been suggested in 2003 that for the 16 nm node, a logic transistor would have a gate length of about 5 nm. In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.

In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a 16 nm SRAM chip.

In September 2011, Hynix announced the development of 15 nm NAND cells.

In December 2012, Samsung Electronics taped out a 14 nm chip.

In September 2013, Intel demonstrated an Ultrabook laptop that used a 14 nm Broadwell CPU, and Intel CEO Brian Krzanich said, "[CPU] will be shipping by the end of this year." However, as of February 2014, shipment had at time erstwhile been delayed further until Q4 2014.

In August 2014, Intel announced details of the 14 nm microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's 14 nm manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 — according to the press release. "Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.

In 2018 a shortage of 14 nm fab capacity was announced by Intel.

Shipping devices

In 2013, SK Hynix began mass-production of 16nm NAND flash, TSMC began 16nm FinFET production, and Samsung began "10nm class" NAND flash production.

On September 5, 2014, Intel launched the first three Broadwell-based processors that belonged to the low-TDP Core M family: Core M-5Y10, Core M-5Y10a, and Core M-5Y70.

In February 2015, Samsung announced that their flagship smartphones, the Galaxy S6 and S6 Edge, would feature 14 nm Exynos systems on chip (SoCs).

On March 9, 2015, Apple Inc. released the Early 2015 MacBook and MacBook Pro, which utilized 14 nm Intel processors. Of note is the i7-5557U, which has Intel Iris Graphics 6100 and two cores running at 3.1 GHz, using only 28 watts.

On September 25, 2015, Apple Inc. released the iPhone 6S & 6S Plus, which were erstwhile equipped with "desktop-class" A9 chips that are fabricated in both 14 nm by Samsung and 16 nm by TSMC (Taiwan Semiconductor Manufacturing Company).

In May 2016, Nvidia released its GeForce 10 series GPUs based on the Pascal architecture, which incorporates TSMC's 16 nm FinFET technology and Samsung's 14 nm FinFET technology.

In June 2016, AMD released its Radeon RX 400 GPUs based on the Polaris architecture, which incorporated 14 nm FinFET technology from Samsung. The technology had at that time been licensed to GlobalFoundries for dual sourcing.

On August 2, 2016, Microsoft released the Xbox One S, which utilized 16 nm by TSMC.

On March 2, 2017, AMD released its Ryzen CPUs based on the Zen architecture, incorporating 14 nm FinFET technology from Samsung which had erstwhile been licensed to GlobalFoundries for GlobalFoundries to build.

The NEC SX-Aurora TSUBASA processor, introduced in October 2017, used a 16nm FinFET process from TSMC and was designed for use with NEC SX supercomputers.

On July 22, 2018, GlobalFoundries announced their 12 nm Leading-Performance (12LP) process, based on a licensed 14LP process from Samsung.

In September 2018, Nvidia released GPUs based on their Turing (microarchitecture), which were made on TSMC's 12 nm process and had a transistor density of 24.67 million transistors per square millimeter.

14 nm process nodes

ITRS Logic Device
Ground Rules (2015)	Samsung	TSMC	Intel	GlobalFoundries	SMIC	Process name	Transistor density (MTr/mm2)	Transistor gate pitch (nm)	Interconnect pitch (nm)	Transistor fin pitch (nm)	Transistor fin width (nm)	Transistor fin height (nm)	Production year
16/14 nm	14LPE	14LPP	11LPP	16FF
(16 nm)	16FF+
(16 nm)	16FFC
(16 nm)	12FFC
(12 nm)	14 nm	14 nm +	14 nm ++	14LPP
(14 nm)	12LP
(12 nm)	12LP+
	32.94	54.38	28.88	33.8	37.5
44.67	30.59	36.71		30
70	78	88	70	84	84		90
56	67	70	52	colspan="2"
42	49	45	42	48		51
8	8	colspan="4"	8	colspan="2"
42	~38	37	42	colspan="2"
2015	2014 Q4	2016 Q1	2018 H2	2013 Q4 risk production
2014 production	2015 Q3	2016 Q2	2017	2014 Q3	2016 H2	2017	2016	2018	2020 Q3

Lower numbers are better, except for transistor density, in which case the opposite is true. Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).

References

(July 23, 2020). "No More Nanometers – EEJournal".
Shukla, Priyank. "A Brief History of Process Node Evolution".
Hruska, Joel. (June 23, 2014). "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists...".
(2016-09-10). "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022".
(2018-03-12). "Life at 10nm. (Or is it 7nm?) And 3nm – Views on Advanced Silicon Platforms".
Richard, O.. (2007). "Sidewall damage in silica-based low-''k'' material induced by different patterning plasma processes studied by energy filtered and analytical scanning TEM". Microelectronic Engineering.
Gross, T.. (2008). "Detection of nanoscale etch and ash damage to nanoporous methyl silsesquioxane using electrostatic force microscopy". Microelectronic Engineering.
Axelrad, V.. (2010). "16nm with 193nm immersion lithography and double exposure". Proc. SPIE.
Noh, M-S.. (2010). "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows". Proc. SPIE.
(August 23, 2010). "Mentor moves tools toward 16-nanometer". EETimes.
(January 17, 2011). "IBM and ARM to Collaborate on Advanced Semiconductor Technology for Mobile Electronics". IBM Press release.
"Intel to build fab for 14-nm chips". EE Times.
[https://www.eetimes.com/document.asp?doc_id=1258701 ''Update: Intel to build fab for 14-nm chips'']
(January 14, 2014). "Intel shelves cutting-edge Arizona chip factory". Reuters.
(May 17, 2011). "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows". AnandTech.
(June 11, 2012). "FinFET: History, Fundamentals and Future". Symposium on VLSI Technology Short Course.
(December 2002). "Digest. International Electron Devices Meeting".
(2005). "Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm [[FinFET]] with elevated source/drain extension".
(December 1, 2003). "Intel scientists find wall for Moore's Law". ZDNet.
"15 Nanometre Memory Tested".
"16nm SRAM produced – Taiwan Today". taiwantoday.tw.
Hübler, Arved. (2011). "Printed Paper Photovoltaic Cells". Advanced Energy Materials.
(December 21, 2012). "Samsung reveals its first 14nm FinFET test chip". Engadget.
(September 10, 2013). "Intel reveals 14nm PC, declares Moore's Law 'alive and well'". The Register.
(February 12, 2014). "Intel postpones Broadwell availability to 4Q14". Digitimes.com.
(August 11, 2014). "Intel Discloses Newest Microarchitecture and 14 Nanometer Manufacturing Process Technical Details". Intel.
(September 6, 2018). "Intel Faces 14nm Shortage As CPU Prices Rise - ExtremeTech".
"History: 2010s".
"16/12nm Technology". [[TSMC]].
(11 April 2013). "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". [[Tom's Hardware]].
Shvets, Anthony. (7 September 2014). "Intel launches first Broadwell processors". CPU World.
"Samsung Announces Mass Production of Industry's First 14nm FinFET Mobile Application Processor".
(2015). "Apple MacBook Pro "Core i7" 3.1 13" Early 2015 Specs". EveryMac.com.
(2015). "Intel Core i7-5557U specifications". CPU World.
Vincent, James. (9 September 2015). "Apple's new A9 and A9X processors promise 'desktop-class performance'". The Verge.
"Talks of foundry partnership between NVIDIA and Samsung (14nm) didn't succeed, and the GPU maker decided to revert to TSMC's 16nm process.".
"Samsung to Optical-Shrink NVIDIA "Pascal" to 14 nm".
(28 July 2016). "AMD Announces RX 470 & RX 460 Specifications; Shipping in Early August". Anandtech.
(November 6, 2015). "GlobalFoundries announces 14nm validation with AMD Zen silicon". ExtremeTech.
"NEC releases new high-end HPC product line, SX-Aurora TSUBASA". NEC.
(August 21, 2018). "Hot Chips 2018: NEC Vector Processor Live Blog". [[AnandTech]].
Schor, David. (2018-07-22). "VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP".
(September 4, 2020). "NVIDIA GeForce RTX 30 Series & Ampere GPUs Further Detailed – GA102/GA104 GPU Specs & RTX 3090, RTX 3080, RTX 3070 Performance & Features Revealed".
"16/12nm Technology".
"PB14LPP-1.0".
"PB12LP-1.1".
Schor, David. (July 22, 2018). "VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP".
Schor, David. (April 16, 2019). "TSMC Announces 6-Nanometer Process".
(November 26, 2019). "7nm vs 10nm vs 14nm: Fabrication Process – Tech Centurion".
(March 30, 2017). "Intel Now Packs 100 Million Transistors in Each Square Millimeter".
Bohr, Mark. (March 28, 2017). "Let's Clear Up the Node Naming Mess".
"Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review".
"SMIC-14nm".
Frumusanu, Andrei. "The Samsung Exynos 7420 Deep Dive – Inside A Modern 14nm SoC".
Frumusanu, Andrei. "Samsung Announces Second-Gen 14nm Low Power Plus (14LPP) Process Now In Mass Production".
Shilov, Anton. "Samsung Details 11LPP Process Technology: 10 nm BEOL Meets 14 nm Elements".
Smith, Ryan. "Intel's 14nm Technology in Detail".
Cutress, Ian. "Intel Announces 7th Gen Kaby Lake: 14nm PLUS, Six Notebook SKUs, Desktop coming in January".
Howse, Brett. "Intel Announces 8th Generation Core "Coffee Lake" Desktop Processors: Six-core i7, Four-core i3, and Z370 Motherboards".
"GLOBALFOUNDRIES 12LP+ FinFET Solution Ready for Production".
Shilov, Anton. "SMIC: 14nm FinFET in Risk Production; China's First FinFET Line To Contribute Revenue by Late 2019".
Shilov, Anton. "SMIC Begins Volume Production of 14 nm FinFET Chips: China's First FinFET Line".
DIGITIMES. (2019-11-14). "SMIC to move 12nm FinFET process to risk production by year-end 2019".
"SMIC starts small-scale mass production of the 12nm process. Has domestic wafer foundry technology caught up with Intel?".
(December 22, 2017). "Nanotechnology is expected to make transistors even '''smaller''' and chips correspondingly '''more powerful'''".
"Intel 14nm Process Technology".
(January 20, 2016). "Samsung's 14 nm LPE FinFET transistors". Electronics EETimes.
"14 nm lithography process – WikiChip".
"16 nm lithography process – WikiChip".
"International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report".
Shilov, Anton. "SMIC Begins Volume Production of 14 nm FinFET Chips: China's First FinFET Line".

Info: Wikipedia Source

This article was imported from Wikipedia and is available under the Creative Commons Attribution-ShareAlike 4.0 License. Content has been adapted to SurfDoc format. Original contributors can be found on the article history page.

international-technology-roadmap-for-semiconductors-lithography-nodes

Want to explore this topic further?

Ask Mako anything about 14 nm process — get instant answers, deeper analysis, and related topics.

Research with Mako

Free with your Surf account

Content sourced from Wikipedia, available under CC BY-SA 4.0.

This content may have been generated or modified by AI. CloudSurf Software LLC is not responsible for the accuracy, completeness, or reliability of AI-generated content. Always verify important information from primary sources.

Report