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ST6 and ST7

8-bit microcontroller product lines from STMicroelectronics

ST6 and ST7

8-bit microcontroller product lines from STMicroelectronics

ST62E40 microcontroller, based on the ST6 architecture

The ST6 and ST7 are 8-bit microcontroller product lines from STMicroelectronics. They are commonly used in small embedded applications like washing machines.

Although they use similar peripherals and are marketed as part of the same product line, the two architectures are actually quite different.

Both have an 8-bit accumulator used for most operations, plus two 8-bit index registers (X and Y) used for memory addressing. Also both have 8-bit instructions followed by up to 2 bytes of operands, and both have support for manipulating and branching on individual bits of memory.

There, the similarities end.

The ST6 is a Harvard architecture with an 8-bit (256 byte) data address space and a separate 12-bit (4096 byte) program space. Operands are always 1 byte long, and some instructions support two operands, such as "move 8-bit immediate to 8-bit memory address". Subroutine calls are done using a separate hardware stack. Data registers (but not the program counter or flags) are memory-mapped.

The ST6's addressing modes are limited to immediate, 8-bit absolute memory address, and register indirect modes (X) and (Y).

The ST7 is a von Neumann architecture with a single 16-bit (64 kiB) address space. The first 256 bytes of RAM (the zero page) have extra flexibility. There are no two-operand instructions except for "test bit and branch". Its registers are not memory-mapped, and it uses general-purpose RAM (plus a stack pointer register) for subroutine calls.

The ST7 supports a wide variety of addressing modes, including base+index and double-indirect.

Three members of the ST6 microcontroller family: ST62E01, ST62E20, ST62E25

ST6 architecture

The ST6 has 64 bytes of RAM and 4096 bytes of program ROM. Larger amounts are accessed by bank-switching the low 2K section of the ROM.

The RAM address space is actually 256 bytes, divided as follows:

  • 0–63: Not implemented
  • 64–127: Bank-switchable window into program ROM and data EPROM.
  • 128–191: General-purpose RAM
  • 192–255: Peripheral control registers (GPIO ports, timers, etc.) The accumulator is mapped at address 255, but is more commonly addressed implicitly.

Not mapped into the address space is a 12-bit program counter and an associated hardware stack (four or six levels deep, depending on model). There are only two status bits (carry and zero), and they are banked based on processor mode, with separate status bits for normal, interrupt and non-maskable interrupt operation.

The first four general-purpose RAM locations are also known as the X, Y, V and W registers, and some instructions can access them using special short addressing modes. The X and Y registers serve as index registers, and can use indirect addressing modes (X) and (Y).

The instruction set consists of one byte of opcode, followed by up to two one-byte operands. The instruction set can be summarized as follows:

76543210b2b3MnemonicCZDescriptionoffsetcolspan=2opc0colspan=4Conditional branches (5-bit PC-relative)imm4c001imm8colspan=4Unconditional branches (12-bit absolute)regc1c101colspan=4Register operations (on X, Y, V or W)opcode01101colspan=4Miscellaneous operationsbitcolspan=2opc011address?colspan=4Bit operations (absolute address only)opcodecolspan=2data111?colspan=4ALU operations with RAM or immediate
offset000JRNZ *address*
offset100JRZ *address*
offset010JRNC *address*
offset110JRC *address*
imm40001imm8
imm41001imm8
00101
reg010101
reg110101
reg011101
reg111101
0000110
1000110
0100110
1100110
0010110
1010110
0110110
1110110
bit00011src
bit10011src
bit01011dst
bit11011dst
opcode00111
opcode01111
opcode10111imm8
opcode11111addr
000src111
100dst111
010src111
110src111
001src111
101src111
011dst111
111dst111

Carry note†: ^ a b Confusingly, different models of the ST6 family use different conventions for the value of the carry bit after a subtraction. ST60 processors use the "carry" convention, which clears the bit if the subtract underflows, while the ST62 and ST63 processors use the "borrow" convention, which sets the bit in that case.

ST7 architecture

The ST7 has six registers: the accumulator, X and Y index registers, stack pointer, program counter, and condition code register. Also, double-indirect addressing allows the zero page of RAM to serve as additional registers. An unusual but useful feature is that an interrupt pushes four of these registers on the stack (A and X as well as the usual PC and CC), and interrupt return restores them.

ALU instructions fall into two categories, two-operand and one-operand.

Two-operand instructions use the accumulator as the first source. The addressing mode specifies the second source, which may be:

  • 8-bit immediate
  • 8-bit absolute address
  • 16-bit absolute address
  • Indexed (X)
  • Indexed plus 8-bit offset (address8,X)
  • Indexed plus 16-bit offset (address16,X) The destination is usually the accumulator, but a few instructions modify the second source. (Immediate operands are forbidden in such cases.)

One-operand instructions use the specified operand for both source and destination. The operand may be:

  • The accumulator A
  • The X register
  • 8-bit absolute address
  • Indexed (X)
  • Indexed plus 8-bit offset (address8,X)

Register plus offset computes a full-width sum, so the 8-bit form may address memory up to 255+255 = 510.

In addition to the above, there are three prefix bytes which may be prepended to any instruction for which they make sense:

  • PDY (0x90) changes all references to the X register to Y. This allows (Y), (address8,Y) and (address16,Y) addressing modes. This affects implicit operands as well, so the "load X" instruction becomes "load Y". A consequence of this is that load X can only use the X-relative addressing modes, and load Y can only use the Y-relative ones.
  • PIX (0x92) adds an indirection step to the instruction. The 8- or 16-bit address following the opcode byte is replaced by an 8-bit address of a memory location which holds an 8- or 16-bit address (the latter in big-endian order). This may then be indexed by the X register as usual. This allows (address8), (address16), ([address8],X) and ([address8.w],X) addressing modes.
  • PIY (0x91) combines the above effects. This allows the ([address8],Y) and ([address8.w],Y) addressing modes. (It may also be used with other modes as part of the "load Y" and "store Y" instructions.)
76543210b2b3MnemonicDescription000ccolspan=3bitvaddress?colspan=2Bit operations0010colspan=4conditionsoff8colspan=2Conditional branches (8-bit relative offset)0colspan=3modecolspan=4opcode?colspan=2One-operand instructions100colspan=5opcodecolspan=2Miscellaneous instructions. None implicitly set the condition codes.1colspan=3modecolspan=4opcodevalue?colspan=2Two-operand instructions A := A op operand
0000bit0
0000bit1
0001bit0
0001bit1
001000
001000
001000
001000
001001
001001
001001
001001
001010
001010
001010
001010
001011
001011
001011
001011
0011opcodeaddr8
0100opcode
0101opcode
0110opcodeaddr8
0111opcode
0mode0000
0mode0001
0mode0010
010000
0mode0011
0mode0100
0mode0101
0mode0110
0mode0111
0mode1000
0mode1001
0mode1010
0mode1011
0mode1100
0mode1101
0mode1110
0mode1111
100000
100000
100000
100000
100001
100001
100001
100001
100010
100010
100010
100010
100011
100011
100011
100100
100100
100100
100100
100101
100101
100101
100101
100110
100110
100110
100110
100111
100111
100111
100111
1010opcodeimm8
1011opcodeaddr8
1100opcodeaddrhi
1101opcodeaddrhi
1110opcodeaddr8
1111opcode
1mode0000
1mode0001
1mode0010
1mode0011
1mode0100
1mode0101
1mode0110
101001
1mode0111
1mode1000
1mode1001
1mode1010
1mode1011
101011
1mode1100
101011
1mode1101
1mode1110
101011
1mode1111

References

References

  1. Datasheet: ST62T00C/T01C from 1998
  2. "2006 EDN Microcontroller/Microprocessor directory, 8-bit microprocessors sorted by Instruction Set Architecture".
  3. (October 2004). "ST6 Family Programming Manual". [[STMicroelectronics]].
  4. (November 2005). "ST7 Family Programming Manual". [[STMicroelectronics]].
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