COP8

Registers and memory map

|} The COP8 uses separate instruction and data spaces (Harvard architecture). Instruction address space is 15-bit (32 KiB maximum), while data addresses are 8-bit (256 bytes maximum, extended via bank-switching).

To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction. Invalid RAM above the stack reads as all-ones, which is an invalid address.

The CPU has an 8-bit accumulator and 15-bit program counter. 16 additional 8-bit registers (R0–R15) and an 8-bit program status word are memory mapped. There are special instructions to access them, but general RAM access instructions may also be used.

The memory map is divided into half RAM and half control registers as follows:

If RAM is not banked, then R15 (S) is just another general-purpose register. If RAM is banked, then the low half of the data address space (addresses 0x00–7F) is directed to a RAM bank selected by S. The special purpose registers in the high half of the data address space are always visible. The data registers at 0xFx can be used to copy data between banks.

RAM banks other than bank 0 have all 128 bytes available. The stack (addressed via the stack pointer) is always on bank 0, no matter how the S register is set.

Control transfers

In addition to 3-byte and instructions which can address the entire address space, 2-byte versions of these instructions, and , can jump within a 4K page. The instruction specifies the low 12 bits, and the high 3 bits of the PC are preserved. (These are intended primarily for models with up to 4K of ROM.) For short-distance branches, there are 63 1-byte instructions, , which perform PC-relative branches from PC−32 to PC+31. This is a 15-bit addition, and no page boundary requirements apply.

There are also jump indirect and load accumulator indirect instructions which use the accumulator contents as the low 8 bits of an address; the high 7 bits of the current PC are preserved.

Conditional branches per se do not exist, nor does the processor provide the traditional ZCVN status flags, although the program status word contains carry and half-carry flags for multi-byte arithmetic. Rather, there are a number of compare-and-skip instructions. For example, compares its two operands, and skips the following instruction if they are unequal. Any instruction may be skipped; it is not limited to branches.

An interesting extension of this mechanism is the return-and-skip instruction, which lets any subroutine conditionally skip the instruction following the call. This provides a very compact way to return a boolean value from a subroutine.

Another feature unique to the COP8 architecture is the instruction. This one-byte instruction compares the low 4 bits of the B (memory pointer) register with a 4-bit immediate constant, and can be used to loop until B has reached the end of a small (up to 16 byte) buffer. There is also a one-byte instruction.

Instruction set

COP8 operands are listed in destination, source order. Most instructions have the accumulator A as one of the operands. The other operand is generally chosen from an 8-bit immediate value, an 8-bit RAM address, or , the RAM address selected by the B register. The and (exchange with accumulator) instructions also support RAM addressing by the X register () and post-inc/decrement variants (, , , ).

Indirect addressing via B is particularly fast, and can be done in the same cycle that the instruction is executed; even is a one-cycle instruction.

On the other hand, absolute RAM addressing is only directly encoded for five instructions: LD A,*addr8*, X A,*addr8*, IFEQ *addr8*,#*imm8*, LD *addr8*,#*imm8*, and DIR *addr8*. The latter is a "direct addressing" opcode prefix which may be prepended to any instruction with a operand, and changes the operand to the specified memory location. (Conditional-skip instructions skip the prefix and following instruction as a pair.) Using with the , and LD [B],#*imm8* instructions is not documented, as the dedicated instructions are more efficient.

All "move" instructions are called (load) even if the destination is a memory address (LD *addr8*,#*imm8*). Unusually, there are no instructions with the accumulator as a source; stores must be done with the instruction which exchanges the accumulator with the memory operand, storing A and loading the previous memory contents.

There are instructions to fetch from tables in ROM. These combine the high 7 bits of the program counter (PCU) with the accumulator, fetch a byte from that address, and place it in the accumulator ( instruction) or the low 8 bits of the program counter PCL ( instruction). Because the next instruction executed must be in the same 256-byte page of ROM as the table itself, a 256-entry table is not possible.

Notable uses

• The COP8 family is employed in the FMU-139 aerial bomb fuze
• The COP822 is employed in the M732A2 artillery fuze

References

References

1. (June 1996). "COP8 Basic Family User's Manual". [[National Semiconductor]].
2. (March 1999). "COP8 Feature Family User's Manual". [[National Semiconductor]]}} Extracted from [[ZIP (file format).
3. Aleaf, Abdul. (July 1996). "Comparison of COP878x to the Enhanced COP8SAx7 Family - Hardware/Software Considerations". [[National Semiconductor]].
4. (January 1997). "COP8SAx Designer's Guide". [[National Semiconductor]].
5. (April 2002). "COP8SBR9/COP8SCR9/COP8SDR98-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout". [[National Semiconductor]].
6. Liberatore, David. (11 May 2006). "FMU-139C/B Electronic Bomb Fuze Design Update".
7. (November 1991). "Application Note 761 - Electronic Fuzing". Texas Instruments.