instruction-processing
Articles
- Control store
- Random logicUnstructured semiconductor logic design
- Instruction cycleBasic instruction cycle in a computer
- Micro-operationLow-level instructions used in some designs to implement complex machine instructions
- Hardware scout
- RunaheadMicroprocessing technique
- Out-of-order executionComputing paradigm to improve computational efficiency
- Instructions per cycleAverage number of instructions executed for each clock cycle
- Register windowCPU architecture feature to improve performance
- Pipeline (computing)Data processing chain
- Pipeline stallDelay in the execution of a processor instruction in a pipeline
- Minimal instruction set computerCPU architecture
- Branch predictorDigital circuit
- Instruction cycleBasic instruction cycle in a computer
- Reservation station
- Random logicUnstructured semiconductor logic design
- Instruction cycleBasic instruction cycle in a computer
- Reservation station
- ScoreboardingInstruction scheduling method
- MicrocodeLayer of hardware-level instructions or data structures
- Control store
- Reservation station
- Tomasulo's algorithmComputer architecture hardware algorithm
- Pipeline stallDelay in the execution of a processor instruction in a pipeline
- Pipeline stallDelay in the execution of a processor instruction in a pipeline
- Slipstream (computer science)
- Anticiparallelism
- Prefetch input queueCPU optimization unit
- Hardware scout
- RunaheadMicroprocessing technique
- Cycles per instructionAspect of CPU performance
- Delay slotInstruction slot being executed without the effects of a preceding instruction
- Control store
- Hardware scout
- RunaheadMicroprocessing technique
- Random logicUnstructured semiconductor logic design
- Interlock (engineering)Feature that makes two mechanisms mutually interdependent
- Random logicUnstructured semiconductor logic design
- Instruction cycleBasic instruction cycle in a computer
- Reservation station
- Hardware scout
- RunaheadMicroprocessing technique
- Pipeline stallDelay in the execution of a processor instruction in a pipeline
- Minimal instruction set computerCPU architecture
- Control store
- Micro-operationLow-level instructions used in some designs to implement complex machine instructions
- Micro-operationLow-level instructions used in some designs to implement complex machine instructions
- Micro-operationLow-level instructions used in some designs to implement complex machine instructions
- Classic RISC pipelineInstruction pipeline
- Hazard (computer architecture)Problems with the instruction pipeline in central processing unit (CPU) microarchitectures