TILE64
title: "TILE64" type: doc version: 1 created: 2026-02-28 author: "Wikipedia contributors" status: active scope: public tags: ["manycore-processors", "very-long-instruction-word-computing", "computer-related-introductions-in-2007"] topic_path: "technology/computing" source: "https://en.wikipedia.org/wiki/TILE64" license: "CC BY-SA 4.0" wikipedia_page_id: 0 wikipedia_revision_id: 0
::data[format=table title="Infobox CPU"]
| Field | Value |
|---|---|
| name | TILE64 |
| produced-start | 2007 |
| slowest | 600 |
| fastest | 900 |
| slow-unit | MHz |
| fast-unit | MHz |
| size-from | 45 nm |
| size-to | 90 nm |
| manuf1 | Tilera |
| numcores | 64 |
| :: |
| name = TILE64 | image = | image_size = | caption = | produced-start = 2007 | produced-end = | slowest = 600 | fastest = 900 | slow-unit = MHz | fast-unit = MHz | fsb-slowest = | fsb-fastest = | fsb-slow-unit = | fsb-fast-unit = | size-from = 45 nm | size-to = 90 nm | manuf1 = Tilera | core1 = | sock1 = | arch = | microarch = | numcores = 64 TILE64 is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor.
The short-pipeline, in-order, three-issue cores implement a MIPS-inspired VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load–store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system.
TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz.
::data[format=table] | [[Image:Tile64.svg|framed|Schematic of the TILE64 processor]] | [[Image:Tile64-Tile.svg|framed|Schematic of a TILE of the TILE64 processor]] | |---|---| ::
According to CTO and co-founder Anant Agarwal, Tilera will target the chip at networking equipment and digital video markets where the demands for computing processing are high.
Support for the TILE64 architecture was added to Linux kernel version 2.6.36 but was dropped in kernel version 4.16. A non-official LLVM back-end for Tilera exists.
References
References
- (August 29, 2009). "Multicore Processors and Systems - Google Books". Springer.
- "Compiler construction - What instruction set is used by Tilera microprocessors?".
- Kingman, Henry. (August 20, 2007). "Massively multicore processor runs Linux". linuxdevices.com.
- Boslet, Mark. (August 20, 2007). "Start-up Tilera to Unveil 64-core chip". San Jose Mercury News.
- (October 20, 2010). "Tilera architecture support". Kernel Newbies.
- (3 April 2018). "Linux 4.16 arrives, erases eight CPUs and keeps melting Meltdown". Situation Publishing.
- [https://www.phoronix.com/scan.php?page=news_item&px=MTE3NzE Tilera TILE64 Back-End For LLVM Published] // [[Phoronix]], September 6, 2012
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