Segment descriptor
title: "Segment descriptor" type: doc version: 1 created: 2026-02-28 author: "Wikipedia contributors" status: active scope: public tags: ["x86-architecture", "operating-system-kernels", "memory-management", "long-stubs-with-short-prose"] topic_path: "technology/operating-systems" source: "https://en.wikipedia.org/wiki/Segment_descriptor" license: "CC BY-SA 4.0" wikipedia_page_id: 0 wikipedia_revision_id: 0
In memory addressing for computer architectures, segment descriptors are a part of the segmentation unit, used for translating a logical address{{efn|IBM uses the term logical address in a different,{{sfn | z-14 | loc = Logical Address | page = 3-5 but related, sense than Intel.}} to a linear address or to the address of a page table. Segment descriptors describe the memory segment referred to in the logical address.
Structure
The segment descriptor contains the following fields:
- A segment base address or page table address
- The segment limit which specifies the segment size
- Access rights information containing the protection mechanism information
- Control bits
Intel
The segment descriptor is 8 bytes long in 80286 and later.
The 80286 segment descriptor
The 80286 segment descriptor has the following form:{{cite book | title = 80286 AND 80287 PROGRAMMER'S REFERENCE MANUAL | id = 210498-005 | year = 1987 | section = Figure 6-3. Code or Data Segment Descriptor (S=1) | section-url = http://bitsavers.org/components/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf#page=115 | page = 6-5 | url = http://bitsavers.org/components/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf | access-date = September 15, 2025 ::data[format=table title="80286 segment descriptor"]
| +1 | Limit15-0 | 0 |
|---|---|---|
| :: |
The x86 and x86-64 segment descriptor
The x86 and x86-64 segment descriptor has the following form:
: [[File:SegmentDescriptor.svg]]
What the fields stand for:
; Base Address : Starting memory address of the segment. Its length is 32 bits and it is created from the lower part bits 16 to 31, and the upper part bits 0 to 7, followed by bits 24 to 31. ; Segment Limit : Its length is 20 bits and is created from the lower part bits 0 to 15 and the upper part bits 16 to 19. It defines the address of the last accessible data. The length is one more than the value stored here. How exactly this should be interpreted depends on the Granularity bit of the segment descriptor. ; G=Granularity : If clear, the limit is in units of bytes, with a maximum of 220 bytes. If set, the limit is in units of 4096-byte pages, for a maximum of 232 bytes. ; D/B : D = Default operand size : If clear, this is a 16-bit code segment; if set, this is a 32-bit segment. : B = Big: If set, the maximum offset size for a data segment is increased to 32-bit 0xffffffff. Otherwise it's the 16-bit max 0x0000ffff. Essentially the same meaning as "D". ; L=Long : If set, this is a 64-bit segment (and D must be zero), and code in this segment uses the 64-bit instruction encoding. "L" cannot be set at the same time as "D" aka "B". (Bit 21 in the image) ; AVL=Available : For software use, not used by hardware (Bit 20 in the image with the label A) ; P=Present : If clear, a "segment not present" exception is generated on any reference to this segment ; DPL=Descriptor privilege level : Privilege level (ring) required to access this descriptor ; S=System Segment : If clear, this is system segment, used to handle interrupts or store LDT segment descriptors. If 1, this is Code/Data segment. ; Type: If set, this is a code segment descriptor. If clear, this is a data/stack segment descriptor, which has "D" replaced by "B", "C" replaced by "E"and "R" replaced by "W". This is in fact a special case of the 2-bit type field, where the preceding bit 12 cleared as "0" refers to more internal system descriptors, for LDT, LSS, and gates. ; C=Conforming : Code in this segment may be called from less-privileged levels. ; E=Expand-Down: If clear, the segment expands from base address up to base+limit. If set, it expands from maximum offset down to limit, a behavior usually used for stacks. ; R=Readable : If clear, the segment may be executed but not read from. ; W=Writable : If clear, the data segment may be read but not written to. ; A=Accessed : This bit is set to 1 by hardware when the segment is accessed, and cleared by software.
IBM S/370 and successors
The S/370, S/370-XA, ESA/370 and ESA/390 segment table entries (STEs) are one word long. All processors running in S/370 mode used the same format, but not all supported the common-segment facility and the protected segment facility. XA introduced a new format and replaced segment protection with page protection.
With z/Architecture the STE is a doubleword.
The S/370 segment-table entry
The segment-table entry for the S/370 has the following form{{cite book | title = IBM System/370 - Principles of Operation | id = GA22-7000-10 | section = Segment-Table Entries | section-url = http://bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf#page=50 | page = 3-25 | date = September 1987 | edition = Eleventh | url = http://bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf | ref = | publisher = IBM | access-date = September 25, 2025 ::data[format=table title="S/370 Segment-Table Entry"]
| TBL | 0000 | Page-Table Origin | P | C | I |
|---|---|---|---|---|---|
| :: |
; Page-Table Origin : Left 21 bits of Page Table Origin (PTO), has 3 zero bits appended ;TBL :Table length in units that are of the maximum allowed size, offset by one unit. ;P :Segment-Protection Bit ;C :Common-Segment Bit ;I :Segment-Invalid Bit
The S/370-XA through S/390 segment-table entry
The segment-table entry for the S/370-XA, ESA/370 and ESA/390 has the following form{{cite book | title = IBM Enterprise Systems Architecture/390 Principles of Operation | id = SA22-7201-08 | section = Segment-Table Entries | section-url = https://publibfp.dhe.ibm.com/epubs/pdf/dz9ar008.pdf#page=86 | page = 3-30 | date = June 2003 | edition = Ninth | url = https://publibfp.dhe.ibm.com/epubs/pdf/dz9ar008.pdf | ref = | publisher = IBM | access-date = September 19, 2025
::data[format=table title="S/370-XA through ESA/390 Segment-Table Entry"]
| 0 | 1 | 25 | 26 | 27 | 28 | 31 |
|---|---|---|---|---|---|---|
| 0 | Page-Table Origin | I | C | TBL | ||
| :: |
; Page-Table Origin : Left 25 bits of PTO, has 6 zero bits appended ;I :Invalid ;C :Common-Segment Bit ;TBL :Table length in 64-byte units, offset by one unit
The z/Architecture segment-table entry
In the original z/Architecture, a segment is always subject to paging and the Segment-Table Entry always points to a page table. However, on a model equipped with the Enhanced-DAT Facility 1, the Enhanced-DAT-enablement control (bit 40) o
The segment-table entry for the z/Architecture has the following forms{{sfn | z14 | loc = Segment-Table Entries | pages = 3-50-3-52
::data[format=table title="z/Architecture Segment-Table Entry (TT=00, FC=0)"]
| 0 | 31 | 32 | 53 | 54 | 55 | 57 | 58 | 59 | 60 | 61 | 62 | 63 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Page-Table Origin | ||||||||||||
| Page-Table Origin (continued) | F | |||||||||||
| C | P | I | C | |||||||||
| S | TT | |||||||||||
| :: |
; Page-Table Origin : Left 53 bits of PTO, has 11 zero bits appended ; FC=0 : Format Control - paged segment ; P : DAT-protection (fetch protect) ; I : Segment-Invalid Bit ; CS : Common-Segment Bit ; TT=00 : Table Type Segment
::data[format=table title="z/Architecture Segment-Table Entry (TT=00, FC=1, EDAT-1)"]
| 0 | 31 | 32 | 43 | 44 | 46 | 47 | 48 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Segment-Frame Absolute Address | ||||||||||||||||||||
| Segment-Frame Absolute Address (continued) | A | |||||||||||||||||||
| V | ACC | F | F | |||||||||||||||||
| C | P | I | ||||||||||||||||||
| E | ||||||||||||||||||||
| P | I | C | ||||||||||||||||||
| S | TT | |||||||||||||||||||
| :: |
; ACCF-Validity Control (AV) : Use ACC to check key ; ACC : Access control key ; F : Fetch protection when AV=1 ; FC=1 : Format Control - points to absolute address ; P : DAT-protection (fetch protect) ; Instruction-Execution-Protection (IEP) Control : Instruction execution prohibited ; I : Segment-Invalid Bit ; CS : Common-Segment Bit ; TT=00 : Table Type Segment
Notes
References
Note that SA22-7832-foo is 0-based but edition is 1-based -- ;z-14 :{{cite book | title = z/Architecture Principles of Operation | id = SA22-7832-14 | date = April 2025 | edition = Fifteenth | ref = | url = https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf | publisher = IBM | access-date = July 3, 2025
References
- Bovet, D.P., & Cesati, M. (2000). ''Understanding the Linux Kernel (First Edition)''. O'Reilly & Associates, Inc.
- Tabak, Daniel. (1995). "Advanced Microprocessors". Mcgraw Hill Publishers.
- (2013). "AMD64 Architecture Programmer's Manual Volume 2: System Programming".
::callout[type=info title="Wikipedia Source"] This article was imported from Wikipedia and is available under the Creative Commons Attribution-ShareAlike 4.0 License. Content has been adapted to SurfDoc format. Original contributors can be found on the article history page. ::