PWRficient

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title: "PWRficient" type: doc version: 1 created: 2026-02-28 author: "Wikipedia contributors" status: active scope: public tags: ["power-microprocessors"] description: "PowerPC variant" topic_path: "general/power-microprocessors" source: "https://en.wikipedia.org/wiki/PWRficient" license: "CC BY-SA 4.0" wikipedia_page_id: 0 wikipedia_revision_id: 0

::summary PowerPC variant ::

::data[format=table title="Infobox CPU"]

Field	Value
name	PA6T-1682M
image	Pwrficient.png
image_size	150
produced-start	2007
produced-end	2008
slowest	1.8
fastest	2.0
size-from	65 nm
designfirm	P.A. Semi
arch	Power ISA (Power ISA v.2.04)
microarch	PA6T
numcores	2
l1cache	64+64 KB/core
l2cache	2 MB/core
::

PWRficient is a microprocessor series by P.A. Semi where the PA6T-1682M was the only one that became an actual product.

PWRficient processors comply with the 64-bit Power ISA, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined to multi-core system-on-a-chip (SoC) designs, combining CPU, northbridge, and southbridge functionality on a single processor die.

Details

The PA6T is the first and only processor core from P.A. Semi, in two distinct product lines: 16xxM dual core and 13xxM/E single core. The PA6T lines differed in L2 cache size, memory controllers, communication functionality, and cryptography offloading features. P.A. Semi planned up to 16 cores.{{cite web |title=PA Semi heads to 16 cores on back of $50m boost |publisher=The Register |url=https://www.theregister.co.uk/2006/05/17/pasemi_core_ti/ |date=2006-05-17 |accessdate=2012-07-02

The PA6T is the first Power ISA core designed from scratch in the previous ten years outside the AIM alliance, which included IBM, Motorola, Freescale, and Apple Inc. Since Texas Instruments was an investors in P.A. Semi, it was suggested that its fabrication plants would have manufactured the PWRficient processors.

PWRficient processors were initially shipped to select customers in February 2007 and were released worldwide in Q4 2007.

P.A. Semi was bought by Apple Inc. in April 2008,{{cite news |title=Apple Buys Chip Designer |work=Forbes |url=https://www.forbes.com/2008/04/23/apple-buys-pasemi-tech-ebiz-cz_eb_0422apple.html |date=2008-04-23 |accessdate=2011-07-05 |first1=Erika |last1=Brown |first2=Elizabeth |last2=Corcoran |first3=Brian |last3=Caulfield |title=Apple will please missile makers by backing PA Semi's chip |publisher=The Register |url=https://www.theregister.co.uk/2008/05/16/pasemi_apple_support/ |date=2008-05-16 |accessdate=2011-07-05 |title=DoD may push back on Apple's P.A. Semi bid |publisher=EETimes |url=http://www.eetimes.com/electronics-news/4076837/DoD-may-push-back-on-Apple-s-P-A-Semi-bid |date=2008-05-23 |accessdate=2011-07-05 |archive-url=https://web.archive.org/web/20101213053945/http://www.eetimes.com/electronics-news/4076837/DoD-may-push-back-on-Apple-s-P-A-Semi-bid |archive-date=2010-12-13 |url-status=dead

Implementation

| name = PA6T-1682M | image = Pwrficient.png | image_size = 150 | caption = | produced-start = 2007 | produced-end = 2008 | slowest = 1.8 | slow-unit = GHz | fastest = 2.0 | fast-unit = GHz | fsb-slowest = | fsb-fastest = | fsb-slow-unit = | fsb-fast-unit = | hypertransport-slowest = | hypertransport-fastest = | hypertransport-slow-unit = | hypertransport-fast-unit = | size-from = 65 nm | size-to = | soldby = | designfirm = P.A. Semi | manuf1 = | core1 = | sock1 = | pack1 = | brand1 = | arch = Power ISA (Power ISA v.2.04) | microarch = PA6T | cpuid = | code = | numcores = 2 | l1cache = 64+64 KB/core | l2cache = 2 MB/core | l3cache = | predecessor = | application = PWRficient processors comprise three parts:

CPU

PA6T

• Superscalar, out-of-order 32-bit/64-bit Power ISA processor core
• Adheres to the Power ISA v.2.04
• Little endian or big endian operation
• 64/64 kB instruction and data L1 caches. 32 GB/s bandwidth.
• Six execution units including a double precision FPU and AltiVec unit
• Hypervisor and virtualization support
• Maximum 7 W at 2 GHz
• 11 million transistors, 10 mm² large @ 65 nm.

Memory system

CONEXIUM

• scalable cross-bar interconnect
• 1–8 SMP cores
• 1–2 L2 caches, 512 KB – 8 MB large. 16 GB/s bandwidth.
• 1–4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
• 64 GB/s peak bandwidth
• MOESI coherency

I/O

ENVOI

• Centralized DMA engine, 32 GB/s bandwidth
• 16–64 SerDes lanes
• XAUI
• PCI Express
• SGMII
• Offload engine for cryptography, RAID, TCP

Users

• Curtiss-Wright planned the 1682M processor for its signal processing systems.
• Mercury Computer Systems planned the 1682M processor for its signal and image processing systems.
• NEC planned the 1682M processor for its storage array systems.
• AmigaOne X1000 has the 1682M processor as CPU.

References

References

1. "Press release". P.A. Semi.
2. "[PATCH v2 00/11] Add Apple M1 support to PASemi i2c driver".
3. http://pasemi.com/news/pr_2007_12_20a.html {{Dead link. (February 2011)
4. (June 7, 2007). "Mercury Computer Systems and P.A. Semi Collaborate to Bring PWRficient Processor to Signal and Image Processing Applications".
5. "NEC pops PA Semi chips into storage gear".
6. "X1000".

::callout[type=info title="Wikipedia Source"] This article was imported from Wikipedia and is available under the Creative Commons Attribution-ShareAlike 4.0 License. Content has been adapted to SurfDoc format. Original contributors can be found on the article history page. ::