ARM Cortex-X925
The ARM Cortex-X925, codenamed "Blackhawk", is a high-performance CPU core designed by Arm and introduced in 2024. It is part of the second-generation ARMv9.2 architecture and is built on a 3 nm process node. The Cortex-X925 is designed to excel in single-threaded instruction per clock (IPC) performance, making it ideal for high-performance mobile computing. ARM states that at ISO-frequency, the Cortex-X925 delivers around 17% higher IPC than the preceding Cortex-X4.
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| General information |
|---|
| 2024 |
| ARM Ltd. |
| 40-bit |
| .mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}1–14 per cluster |
| 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
| 2048–3072 KiB per core |
| 512 KiB – 32 MiB (optional) |
| ARM Cortex-X925 |
| ARMv9.2-A |
| Blackhawk |
| ARM Cortex-A725 |
| ARM Cortex-X4 |
| ARM C1-Ultra |
The ARM Cortex-X925, codenamed "Blackhawk", is a high-performance CPU core designed by Arm and introduced in 2024. It is part of the second-generation ARMv9.2 architecture and is built on a 3 nm process node. The Cortex-X925 is designed to excel in single-threaded instruction per clock (IPC) performance, making it ideal for high-performance mobile computing. ARM states that at ISO-frequency, the Cortex-X925 delivers around 17% higher IPC than the preceding Cortex-X4.
- 10-wide decode and dispatch width: This allows the core to process more instructions per cycle, increasing overall throughput.
- Doubled instruction window size: This reduces stalls and improves the efficiency of the execution pipeline.
- Increased L1 instruction cache (I$) bandwidth: The core features a 2x increase in L1 I$ bandwidth, ensuring quick instruction fetch and decode.
- Enhanced branch prediction unit: Techniques such as folded-out unconditional direct branches reduce mispredicted branches, leading to fewer pipeline flushes and higher sustained IPC.
- Support for ARMv9.2-A instruction set: The core supports A64 instruction set and AArch64 execution state at all exception levels.
- Scalable Vector Extension (SVE) and SVE2: These extensions provide advanced SIMD and floating-point support.
- Error protection: The core includes error protection on L1 instruction and data caches, L2 cache, and MMU Translation Cache (MMU TC) with parity or ECC.
The Cortex-X925 is designed to be used in both homogeneous and heterogeneous DynamIQ™ clusters, providing flexibility in various system configurations.
Released in 2024 as part of Arm's "total compute solution." It serves as the successor of ARM Cortex-X4. X-series CPU cores generally focus on high performance, and can be grouped with other ARM cores, such as ARM Cortex-A725 and/or ARM Cortex-A520 in a System-on-Chip (SoC).
| uArch | Cortex-A78 | Cortex-X1 | Cortex-X2 | Cortex-X3 | Cortex-X4 | Cortex-X925 |
|---|---|---|---|---|---|---|
| Hercules | Hera | Matterhorn-ELP | Makalu-ELP | Hunter-ELP | Blackhawk | |
| ARMv8.2 | ARMv9 | ARMv9.2 | ||||
| ~3.0 GHz | ~3.25 GHz | ~3.4 GHz | ~3.8 GHz | |||
| 4 | 5 | 6 | 10 | |||
| 6/cycle | 8/cycle | 10/cycle | ||||
| 2× 160 | 2× 224 | 2× 288 | 2× 320 | 2× 384 | 2× 768 | |
| 1536 | 3072 | 1536 | None | |||
| 32+32 kiB | 64+64 kiB | |||||
| 128–512 kiB | 256–1024 kiB | 512–2048 kiB | 2048–3072 kiB | |||
| 0–8 MiB | 0–16 MiB | 0–32 MiB |
- MediaTek • Dimensity 9400/9400+
- Samsung • Exynos 2500
- Nvidia • GB10 Superchip
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